1. Field of the Invention
The present invention relates to a semiconductor device and a method for setting a delay time, and in particular to a semiconductor device and a method for setting a delay time which can adjust a timing of outputting a signal.
This application is based on Japanese Patent Application No. 10-106073, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, MPUs (Micro Processing Units) and logic circuits connected thereto have come to operate at a significantly high speed, and are required to operate in general at 100 to 300 MHz. Signals from these MPUs are generated based on a clock signal, whose period is 3 to 10 ns, and which will be required to have an even higher frequency in the future.
When a signal is transferred through a logic gate, a delay time may be irregular because the transfer speed, which corresponds to the delay time, may be altered because of irregularities in manufacturing transistors of the logic gate (irregularity in threshold voltages Vt defining the performances of the transistors or in the gate lengths L), in drive performance, in unwanted capacities which lead to loads, in operation temperatures, and in operation voltages. Because of the irregularity in delay time, inaccurate data may be latched or results of the logical operation may become inaccurate, resulting in abnormal operations of the semiconductor device.
The timing of outputting the signals from the semiconductor device must be within a time defined in a specified standard which relates to periphery devices to be connected. To secure co-operation between the semiconductor devices (devices on a board), a signal from one device must be output within a specified time of period so as to allow the other devices to receive the signal reliably. That is, the signal must be output within a maximum delay time and within a minimum delay time with respect to a reference signal.
When the signal is not within these delay times, the output signal may be changed prior to the reference signal, and the semiconductor device cannot receive the signal or may accidentally receive the next signal. Conversely, when the change in the output signal is delayed, the semiconductor device cannot receive an accurate signal or may receive the previous signal.
In general, semiconductor manufacturers tests their products before shipment to confirm whether timings of output signals satisfy the standard. Although when many inferior products are found, the cost may be undesirably increased, techniques for increasing uniformity in products cannot keep pace with the improvement of the operation speeds of the semiconductor devices. It is therefore difficult to achieve the specified minimum and maximum output delay times only by improving the manufacturing process.
The problem in semiconductor design is how to set the delay time to satisfy the standard even when irregularity in products occurs during the manufacturing process. For example, even when irregularity in delay time is 10 ns in a semiconductor device operating at 10 MHz of clock, it does not matter because the clock cycle is 100 ns. When the clock period is 100 MHz and irregularity in delay time is 10 ns, the device cannot function because the clock period is 10 ns.
Japanese Patent Application, First Publication No. 9-181580, discloses a process for adjusting a delay time by the circuitry design of a semiconductor device. In this background art, the semiconductor device includes a delay circuit in which a plurality of delay gates are serially connected. Each AND gate, which can be opened and closed based on control signals, is provided before a delay gate. Before assembling the system, the delay time is measured, and some of delay gates are set to output signals. Then, delay gates which are not in use are searched, and are set to inhibit transmission of pulses by closing the corresponding AND gates.
FIG. 7 is a block diagram showing a prior delay generation circuit in a semiconductor device of the back ground art, and FIG. 8 is a diagram explaining a problem in a prior measurement process. As shown in FIG. 7, the delay generation circuit 33 in the semiconductor device 32 comprises four delay circuits 12a to 12d, a mode switch 13, a selector switch 14, an output switch 15, and a programable read only memory 17 (hereinafter referred to as PROM).
The semiconductor device 32 has five terminals, which are a reference pulse input terminal 19, an operation mode input terminal 20, an output terminal 21, a write terminal 22, and a selection signal input terminal 27. Through these terminals, a semiconductor tester 23 is connected to the semiconductor device 32. The tester 23 includes a memory 23a for storing a measurement result.
The selector switch 14 has four selector contacts 14a to 14d. The first selector contact 14 is connected to a connection point between the first delay circuit 12a and the second delay circuit 12b, the second selector contact 14b is connected to a connection point between the second delay circuit 12b and the third delay circuit 12c, the third selector contact 14c is connected to a connection point between the third delay circuit 12c and the fourth delay circuit 12d, and the fourth selector contact 14 is connected to the output terminal of the fourth delay circuit 12d. The selector switch 14 is operated based on a selection signal input from the output switch 15.
The input to the first delay circuit 12a is connected to the mode switch 13. The mode switch 13 has two selector contacts. The first selector contact 13a receives a reference pulse signal c output from the tester 23, and the second selector contact 13b receives a signal output from an internal circuit. The output switch 15 has two selector contacts. The first selector contact 15a receives a selection signal a via a selection signal input terminal 27 from the tester 23, and the second selector contact 15b receives the output from the PROM 17.
The reference pulse signal c output from the tester 23 is input via the reference pulse input terminal 19 to the first selector contact 13a. An operation mode signal m is output from the tester 23, and is input via the operation mode input terminal 20 to the mode switch 13 and to the output switch 15. A PROM write signal r is input via the write terminal 22 to the PROM 17. The selection signal a is input via the selection signal input terminal 27 to the first selector contact 15a of the output switch 15. The selector switch 14 outputs a delay signal d via the output terminal 21 to the tester 23.
The prior delay generation circuit 33 can set a delay time in a test mode so that the delay time does not exceed a specified delay time T. When the test mode terminates and a normal mode starts, the internal circuit in the semiconductor device 32 outputs signals via the delay generation circuit 33 whose delay time is set to a desired value.
In the prior art, the delay generation circuit 33 performs the test when the operation mode signal m from the tester 23 is a second logic level (hereinafter referred to as "0"), and enters the normal mode when the operation mode signal m is a first logic level (hereinafter referred to as "1"). That is, when the operation mode signal m is 0, the mode switch 13 connects the movable contact 13c to the first selector contact 13a, and the output switch 15 connects the movable contact 15c to the first selector contact 15a. When the operation mode signal m is 1, the mode switch 13 connects the movable contact 13c to the second selector contact 13b, and the output switch 15 connects the movable contact 15c to the second selector contact 15b.
The first to fourth delay circuits 12a to 12d have delay times Ta to Td, respectively. The delay times Ta, Tb, Tc, and Td are added to the signal passing successively through the delay circuits 12a to 12d.
In the test mode, the reference pulse signal c output from the tester 23 is input via the mode switch 13 to the first delay circuit 12a as the reference signal q, and timings of the pulses output from the first to fourth delay circuits 12a to 12d are checked. In the normal operation, the PROM 17 outputs the written selection information to the selector switch 14, and one of the delay circuits 12a to 12d selected by the selector switch 14 outputs the signal via the output terminal 21 to the tester 23.
The reference signal q is input via the mode switch 13 to the first delay circuit 12a, which outputs a delay signal d1 that is delayed from the input reference signal q by the delay time Ta, to the second delay circuit 12b and to the first selector contact 14a. The second delay circuit 12b, which receives the delay signal d1, outputs a delay signal d2 with the delay time (Ta+Tb) that is delayed from the delay signal d1 by the delay time Tb, to the third delay circuit 12c and to the second selector contact 14b.
The third delay circuit 12c, which receives the delay signal d2, outputs a delay signal d3 with the delay time (Ta+Tb+Tc) that is delayed from the delay signal d2 by the delay time Tc, to the fourth delay circuit 12d and to the third selector contact 14c. The fourth delay circuit 12c, which receives the delay signal d3, outputs a delay signal d4 with the delay time (Ta+Tb+Tc+Td) that is delayed from the delay signal d3 by the delay time Td, to the fourth selector contact 14d.
The operation of the delay generation circuit 33 of the prior semiconductor device 32 will be explained.